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_______________ge ne ra l de sc ript ion the max782 is a system-engineered power-supply con- troller for notebook computers or similar battery-p owered equipment. it provides two high-performance step-d own (buck) pulse-width modulators (pwms) for +3.3v and +5v, and dual pcmcia vpp outputs powered by an integral fly- back winding controller. other functions include d ual, low- dropout, micropower linear regulators for cmos/rtc back- up, and three precision low-battery-detection compa rators. high efficiency (95% at 2a; greater than 80% at loa ds from 5ma to 3a) is achieved through synchronous rec ti- fication and pwm operation at heavy loads, and idle - mode tm operation at light loads. it uses physically small components, thanks to high operating frequen- cies (300khz/200khz) and a new current-mode pwm architecture that allows for output filter capacito rs as small as 30f per ampere of load. line- and load-t ran- sient response are terrific, with a high 60khz unit y-gain crossover frequency allowing output transients to b e corrected within four or five clock cycles. low sy stem cost is achieved through a high level of integratio n and the use of low-cost, external n-channel mosfets. t he integral flyback winding controller provides a low- cost, +15v high-side output that regulates even in the absence of a load on the main output. other features include low-noise, fixed-frequency p wm operation at moderate to heavy loads and a synchron iz- able oscillator for noise-sensitive applications su ch as electromagnetic pen-based systems and communicat- ing computers. the max782 is a monolithic bicmos i c available in fine-pitch, ssop surface-mount package s. _______________________applic a t ions notebook computers portable data terminals communicating computers pen-entry systems ___________________________fe a t ure s ? dual pwm buck controllers (+3.3v and +5v) ? dual pcmcia vpp outputs (0v/5v/12v) ? three precision comparators or level translators ? 95% efficiency ? 420a quiescent current;70a in standby (linear regulators alive) ? 5.5v to 30v input range ? small ssop package ? fixed output voltages available: 3.3 (standard)3.45 (high-speed pentium?) 3.6 (powerpc?) ______________orde ring i nform a t ion m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ________________________________________________________________ maxim integrated products 1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ss3 cs3 fb3 dh3 lx3 bst3 lx5 dl3 v+ vl fb5 pgnd dl5 bst5 sync ref gnd vppb vdd vppa q1 q2 q3 vh d3 d2 d1 on3 ssop top view max782 22 21 20 19 15 16 17 18 on5 dh5 cs5 ss5 db0 db1 da0 da1 __________________pin configura t ion max782 5.5v to 30v vpp control on3 on5 sync power section suspend power low-battery warning vpp (0v/5v/12v) p memory peripherals +3.3v +5v dual pcmcia slots 4 vpp (0v/5v/12v) ______typic a l applic a t ion dia gra m ca ll t oll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 for fre e sa m ple s or lit e ra t ure . 19-0146; rev 2; 5/94 part temp. range pin-package max782cbx 0c to +70c 36 ssop max782rcbx 0c to +70c 36 ssop max782scbx 0c to +70c 36 ssop ? idle-mode is a trademark of maxim integrated produc ts. pentium is a trademark of intel . powerpc is a trademark of ibm. evaluation kit information included ordering information continued on last page. v out 3.3v 3.45v 3.6v downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 2 _______________________________________________________________________________________ v+ to gnd .......................................... .......................-0.3v, +36v pgnd to gnd........................................ ................................2v vl to gnd .......................................... .........................-0.3v, +7v bst3, bst5 to gnd .................................. ................-0.3v, +36v lx3 to bst3........................................ .........................-7v, +0.3v lx5 to bst5........................................ .........................-7v, +0.3v inputs/outputs to gnd (d1-d3, on5, ref, sync, da1, da0, db1, db0, on5, ss5, cs5, fb5, cs3, fb3, ss3, on3) ..........-0.3v, (vl + 0.3v) vdd to gnd......................................... ........................-0.3v, 20v vppa, vppb to gnd.................................. ...-0.3v, (vdd + 0.3v) vh to gnd .......................................... .........................-0.3v, 20v q1-q3 to gnd....................................... ..........-0.3v, (vh + 0.3v) dl3, dl5 to pgnd................................... ........-0.3v, (vl + 0.3v) dh3 to lx3 ......................................... .........-0.3v, (bst3 + 0.3v) dh5 to lx5 ......................................... .........-0.3v, (bst5 + 0.3v) ref, vl, vpp short to gnd.......................... ..............momentary ref current........................................ .................................20ma vl current ......................................... ..................................50ma vppa, vppb current ................................. ........................100ma continuous power dissipation (t a = +70c) ssop (derate 11.76mw/c above +70c) ............... ....941mw operating temperature ranges: max782cbx/max782__cbx.............................. .0c to +70c max782ebx/max782__ebx ............................-4 0c to +85c storage temperature range .......................... ...-65c to +160c lead temperature (soldering, 10sec) ................ .............+300c electrical characteristics (v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0ma, on3 = on5 = 5v, other digital input levels a re 0v or +5v, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the devic e. these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. absolute maximum ratings v max782s max782r max782 fb3 output voltage 3.46 3.65 3.75 0mv < (cs3-fb3) < 70mv, 6v < v+ < 30v (includes load and line regulation) 3.32 3.50 3.60 parameter conditions min typ max units current-limit voltage cs5-fb5 (vdd < 13v, flyback mode) -50 -100 -160 mv cs3-fb3 or cs5-fb5 line regulation either controller (v+ = 6v to 30v) 0.03 %/v load regulation either controller (cs_ - fb_ = 0mv to 70mv) 2 % ss3/ss5 source current 2.5 4.0 6.5 a ss3/ss5 fault sink current 2 ma vdd regulation setpoint falling edge, hysteresis = 1% v fb5 output voltage 4.80 5.08 5.20 v 3.17 3.35 3.46 input supply range 5.5 30 v vdd shunt setpoint rising edge, hysteresis = 1% v vdd shunt current vdd = 20v 23 ma quiescent vdd current 140 300 a vdd off current 15 30 a program to 12v, 13v < vdd < 19v, 0ma < i l < 60ma 11.6 12.1 12.5 0mv < (cs5-fb5) < 70mv, 6v < v+ < 30v (includes load and line regulation) vdd = 18v, on3 = on5 = 5v, vppa/b programmed to 12v with no external load program to 5v, 13v < vdd < 19v, 0ma < i l < 60ma 4.85 5.05 5.20 vppa/vppb output voltage program to 0v, 13v < vdd < 19v, -0.3ma < i l < 0.3ma -0.3 0.3 v vppa/vppb off input current program to hi-z, vdd = 19v, 0v < vpp < 12v 35 a vdd = 18v, on3 = on5 = 5v, vppa/b programmed to hi-z or 0v 18 20 13 14 80 100 120 +3.3v and 5v step-down controllers 15v flyback controller pcmcia regulators (note 1) v v downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs _______________________________________________________________________________________ 3 parameter conditions min typ max units d1-d3 trip voltage falling edge, hysteresis = 1% q1-q3 output low voltage vl output voltage ref fault lockout voltage falling edge 2.4 3.2 on5 = on3 = 0v, 5.5v < v+ < 30v, 0ma < i l < 25ma v ref output voltage no external load (note 2) 3.24 3.36 v 4.5 5.5 ref load regulation 0ma < i l < 5ma 30 75 mv v+ standby current 70 110 a 1.61 1.69 v d1-d3 input current d1 = d2 = d3 = 0v to 5v v d1 = d2 = d3 = da0 = da1 = db0 = db1 = 0v, fb5 = cs5 = 5.25v, fb3 = cs3 = 3.5v 6.0 8.6 100 mw v+ off current na fb5 = cs5 = 5.25v, vl switched over to fb5 30 60 a q1-q3 source current vh = 15v, q1-q3 forced to 2.5v 12 20 30 a q1-q3 sink current vl fault lockout voltage vh = 15v, q1-q3 forced to 2.5v 200 500 1000 a q1-q3 output high voltage i source = 5a, vh = 3v vh-0.5 v i sink = 20a, vh = 3v 0.4 v quiescent vh current vh = 18v, d1 = d2 = d3 = 5v, no external load falling edge, hysteresis = 1% 3.6 4.2 v 61 0 a vl/fb5 switchover voltage rising edge of fb5, hysteresis = 1% 4.2 4.7 v note 1: output current is further limited by maximum allowa ble package power dissipation. note 2: since the reference uses vl as its supply, v+ line regulation error is insignificant. electrical characteristics (continued) (v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0ma, on3 = on5 = 5v, other digital input levels a re 0v or +5v, t a = t min to t max , unless otherwise noted.) quiescent power consumption (both pwm controllers on) d1 = d2 = d3 = on3 = on5 = da0 = da1 = db0 = db1 = 0v, v+ = 30v sync low pulse width 200 ns sync high pulse width 200 ns oscillator frequency sync = 0v or 5v 170 200 230 khz sync = 3.3v 270 300 330 maximum duty cycle sync = 0v or 5v 92 95 % sync = 3.3v 89 92 oscillator sync range 240 350 khz sync rise/fall time not tested 200 ns input low voltage on3, on5, da0, da1, db0, db1, sync 0.8 v on3, on5, da0, da1, db0, db1 2.4 input current on3, on5, da0, da1, db0, db1, v in = 0v or 5v 1 a dl3/dl5 sink/source current dl3, dl5 forced to 2v 1 a dl3/dl5 on resistance high or low 7 dh3/dh5 on resistance high or low, bst3-lx3 = bst5-lx5 = 4.5v 7 input high voltage sync vl-0.5 v dh3/dh5 sink/source current bst3-lx3 = bst5-lx5 = 4.5v, dh3, dh5 forced to 2v 1 a internal regulator and reference comparators oscillator and inputs/outputs downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 4 _______________________________________________________________________________________ __________________________________________typic a l o pe ra t ing cha ra c t e rist ic s (circuit of figure 1, transpower transformer type t ti5870, t a = +25c, unless otherwise noted.) 100 70 0.001 0.1 10 efficiency vs. +3. 3v output current, 200khz 80 +3.3v output current (a) efficiency (% ) 90 +5v on, +5v load = 0ma i dd = 0ma, components of table 5 v in = 6v v in = 10v v in = 15v 0.01 1 10 0.01 510 20 30 i dd output current vs. input voltage coiltronix ctx03-12062 transform er 0.1 1 input voltage (v) i dd load current (a) 15 25 +3v load = 0ma r sense = 0.020 +5v load = 0a-1a +5v load = 3a 100 70 0.001 0.1 10 efficiency vs. +5v output current, 200khz 80 +5v output current (a) efficiency (% ) 90 0.01 1 v in = 6v v in = 15v v in = 10v components, of table 5. sync = 0v, +3.3v off, i dd = 0ma 10000 10 0 5 15 25 quiescent input current vs. input voltage 100 1000 input voltage (v) input current ( a) 10 20 30 +3.3v load = +5v load = 0ma +5v, +3v on +5v, +3v off 100 70 0.001 0.01 1 efficiency vs. +5v output current, 300khz 80 90 +5v output current (a) efficiency (% ) 0.1 10 i dd = 0ma +3.3v off v in = 30v v in = 15v v in = 6v 100 70 0.001 0.01 1 efficiency vs. +3. 3v output current, 300khz 80 90 +3.3v output current (a) efficiency (% ) 0.1 10 v in = 30v v in = 15v v in = 6v i dd = 0ma +5v on +5v load = 0ma 8 5 0.01 0.1 10 +5v output current vs. m inim um input voltage, 200khz 6 7 +5v load current (a) minimum input voltage (v) 1 9 components of table 4, sync = 0v i dd = 0ma i dd = 60ma i dd = 140ma i dd = 300ma 9 5 0.01 0.1 10 +5v output current vs. m inim um input voltage, 300khz 6 7 +5v output current (a) minimum input voltage (v) 1 8 i dd = 300ma i dd = 140ma i dd = 60ma i dd = 0ma 1000 0.1 100 a 10ma 1a switching frequency vs. load current 10 load current switching frequency (khz) 100 1ma 100ma circuit of figure 1, sync = ref (300khz) on3 = on5 = 5v +5v, v in = 7.5v 1 +5v, v in = 30v +3.3v, v in = 7.5v downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs _______________________________________________________________________________________ 5 horizontal = 500ns/div +5v output current = 1a input voltage = 16v pulse-width m odulation m ode waveform s lx voltage 10v/div +5v output voltage 50mv/div _____________________________typic a l ope ra t ing cha r a c t e rist ic s (c ont inue d) (circuit of figure 1, transpower transformer type t ti5870, t a = +25c, unless otherwise noted.) horizontal = 5 s/div +5v output current = 42ma input voltage = 16v idle-m ode waveform s lx voltage 10v/div +5v output voltage 50mv/div horizontal = 200 s/div v in = 15v +3. 3v load-transient response +3.3v output 50mv/div 3a 0a load current horizontal = 200 s/div v in = 15v +5v load-transient response +5v output 50mv/div 3a 0a load current downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 6 _______________________________________________________________________________________ horizontal = 20 s/div i load = 2a +5v line-transient response, rising v in , 10v to 16v 2v/div +5v output 50mv/div horizontal = 20 s/div i load = 2a +5v line-transient response, falling v in , 16v to 10v 2v/div +5v output 50mv/div _____________________________typic a l ope ra t ing cha r a c t e rist ic s (c ont inue d) (circuit of figure 1, transpower transformer type t ti5870, vdd 13v, t a = +25c, unless otherwise noted.) horizontal = 20 s/div i load = 2a +3. 3v line-transient response, rising +3.3v output 50mv/div v in , 10v to 16v 2v/div horizontal = 20 s/div i load = 2a +3. 3v line-transient response, falling +3.3v output 50mv/div v in , 16v to 10v 2v/div downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs _______________________________________________________________________________________ 7 name function on3 logic input to turn on +3.3v. logic high turns on the regulator. connect to vl for automatic start-u p. d1 #1 level-translator/comparator noninverting input. inverting comparator input is internally connected to 1.650v. controls q1. connect to gnd if unused. d2 1 2 d3 vh q3 q2 3 4 5 q1 #1 level-translator/comparator output. sources 20 a from vh when d1 is high. sinks 500a to gnd when d1 is low, even with vh = 0v. vppa 0v, 5v, 12v, hi-z pcmcia vpp output. sources up to 60ma. controlled by da0 and da1. 6 7 8 9 ___________________________________________________ ___________pin de sc ript ion pin vdd 15v flyback input (feedback). a weak shunt regulat or conducts 3ma to gnd when vdd exceeds 19v. also the supply input to the vpp regulators. 10 vppb 0v, 5v, 12v, hi-z pcmcia vpp output. sources up to 60ma. controlled by db0 and db1. 11 gnd low-current analog ground 12 intel 82365 compatible pcmcia vpp control inputs (s ee table 1) 15-18 sync 14 ref 13 oscillator frequency control and synchronization in put: connect to vl or to gnd for f = 200khz; conne ct to ref for f = 300khz. for external synchronizatio n in the 240khz to 350khz range, a high-to-low tran si- tion causes the start of a new cycle. da1, da0, db1, db0 #2 level-translator/comparator output. sources 20 a from vh when d2 is high. sinks 500a to gnd when d2 is low, even with vh = 0v. #3 level-translator/comparator output. sources 20 a from vh when d3 is high. sinks 500a to gnd when d3 is low, even with vh = 0v. external supply input for level-translator/comparat or. for n-channel fet drive, connect to vdd or ext ernal +13v to +18v supply. for low-battery comparators, connect to +3.3v or +5v (or to vl/ref). #3 level-translator/comparator noninverting input. inverting comparator input is internally connected to 1.650v. controls q3. connect to gnd if unused. #2 level-translator/comparator noninverting input. inverting comparator input is internally connected to 1.650v. controls q2. connect to gnd if unused. logic input to turn on +5v. logic high turns on th e regulator. connect to vl for automatic startup. 19 on5 ss5 20 cs5 +5v-supply current-sense input. +100mv = current l imit in buck mode, -100mv = current limit in flybac k mode (where the 100mv are referenced to fb5). 21 dh5 +5v-supply external mosfet high-side switch-drive o utput 22 +5v-supply soft-start control input. ramp time to full current limit is 1ms/nf of capacitance to gnd. 3.3v reference output. sources up to 5ma for exter nal loads. bypass to gnd with 1f/ma load or 0.22f minimum. 23 lx5 +5v-supply inductor connection downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 8 _______________________________________________________________________________________ _________________________________________________pi n de sc ript ion (c ont inue d) pin name function dh3 bst5 +5v-supply boost capacitor connection (0.1f to lx5 ) +3.3v-supply external mosfet high-side switch-drive output dl5 +5v-supply external mosfet synchronous-rectifier dr ive output 33 pgnd power ground fb3 24 25 +3.3v-supply feedback and low-side current-sense te rminal fb5 +5v-supply feedback input and low-side current-sens e terminal 34 vl internal 5v-supply output. bypass with 4.7f. thi s pin is linearly regulated from v+ or switched to the +5v output to improve efficiency. vl is always on and can source up to 5ma for external loads. v+ main (battery) input: 5.5v to 30v dl3 +3.3v-supply external mosfet synchronous-rectifier drive output 26 27 28 bst3 +3.3v-supply boost capacitor connection (0.1f to l x3) lx3 +3.3v-supply inductor connection 29 30 31 32 ss3 +3.3v-supply soft-start control input. ramp time t o full current limit is 1ms/nf of capacitance to gn d. 36 cs3 +3.3v-supply current-sense input. maximum is +100m v referenced to fb3. 35 table 1. truth table for vpp control pins d_0 d_1 vpp_ 0 0 1 1 0 1 0 1 0v 5v 12v hi-z _______________de t a ile d de sc ript ion the max782 converts a 5.5v to 30v input to five out puts (figure 1). it produces two high-power, switch-mod e, pulse-width modulated (pwm) supplies, one at +5v an d the other at +3.3v. these two supplies operate at either 200khz or 300khz, allowing extremely small external components to be used. output current capability depends on external components, and can exceed 5a on each supply. a 15v high-side (vdd) supply is al so provided, delivering an output current that can exc eed 300ma, depending on the external components chosen. two linear regulators supplied by the 15v vdd line cre- ate programmable vpp supplies for pcmcia slots. these supplies (vppa, vppb) can be programmed to be grounded or high impedance, or to deliver 5v or 12v at up to 60ma. an internal 5v, 25ma supply (vl) and a 3.3v, 5ma re f- erence voltage (ref) are also generated, as shown i n figure 2. fault-protection circuitry shuts off the pwm and high-side supply when the internal supplies los e regulation. three precision comparators are included. their ou t- put stages permit them to be used as level translat ors for driving high-side external power mosfets: for example, to facilitate switching vcc lines to pcmci a slots. downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs _______________________________________________________________________________________ 9 +3 .3 v supply the +3.3v supply is produced by a current-mode pwm step-down regulator using two small n-channel mosfe ts, a catch diode, an inductor, and a filter capacitor. efficiency is greatly enhanced by the use of the se cond mosfet (connected from lx3 to pgnd), which acts as a synchronous rectifier. a 100nf capacitor connect ed to bst3 provides the drive voltage for the high-sid e (upper) n-channel mosfet. a current limit set by an external sense resistor p revents excessive inductor current during start-up or under short-circuit conditions. a soft-start capacitor c an be chosen to tailor the rate at which the output ramps up. this supply can be turned on by connecting on3 to logic high, or can be turned off by connecting on3 to gnd. all logic levels are ttl and cmos compatible. +5 v supply the +5v output is produced by a current-mode pwm step-down regulator similar to the +3.3v supply. t his supply uses a transformer primary as its inductor, the secondary of which is used for the high-side (vdd) supply. it also has current limiting and soft-star t. it can be turned off by connecting on5 to gnd, or turned o n by connecting on5 to logic high. the +5v supplys dropout voltage, as configured in figure 1, is typically 400mv at 2a. as v in approaches 5v, the +5v output gracefully falls with v in until the vl regulator output hits its undervoltage lockout thre shold. at this point, the +5v supply turns off. the default frequency for both pwm controllers is 300khz (with sync connected to ref), but 200khz may be used by connecting sync to gnd or vl. vppa da0 da1 db0 db1 bst3 dh3 lx3 dl3 cs3 fb3 ss3 on3 on5 sync vppb vdd bst5 dh5 lx5 dl5 cs5 fb5 ss5 vh d1-d3 q1-q3 9 11 10 24 22 23 25 21 27 20 5 2, 3, 4 8, 7, 6 16 15 18 17 31 33 32 30 35 34 36 1 19 14 gnd ref pgnd 29 28 12 13 26 battery input 5.5v to 30v (note 1) vpp control inputs c1 33 f d1a 1n4148 c5 n1 l1 10 h r1 25m +3.3v at 3a c14 150 f c7 150 f d3 1n5819 n3 c9 0.01 f +3.3v on/off +5v on/off osc sync c3 1 f c2 4.7 f c11 1 f c10 1 f d1b 1n4148 c4 0.1 f d2 ec11fs1 n2 1:2.2 l2 10 h d4 1n5819 n4 r2 20m c12 2.2 f c6 330 f +5v at 3a c8 0.01 f 3 3 comparator supply input comparator inputs comparator outputs 3.3v at 5ma +5v at 5ma 0v, 5v, 12v +15v at 300ma, see high-side supply (vdd) section. 0v, 5v, 12v max782 v+ vl c13 33 f n1- n4 = si9410dy note 1: battery voltage range 6.5v to 30v with components shown see low-voltage (6-cell) operation section. note 2: see figure 5. (note 2) (note 2) 0.1 f figure 1. max782 application circuit downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 10 ______________________________________________________________________________________ fb3 cs3 3.3v pwm controller (see fig. 3) dh3 bst3 lx3 dl3 ss3 fb5 cs5 5v pwm controller (see fig. 3) dh5 bst5 lx5 dl5 ss5 on3 on5 +5v ldo linear regulator +3.3v reference 300khz/200khz oscillator vdd q3 q2 q1 v+ vl ref gnd sync vppa da0 da1 vppb db0 db1 d3 d2 d1 vh 1.65v 1.65v 1.65v linear regulator linear regulator 5v 3.3v 4.5v standby 4v 2.8v 13v to 19v fault on on vdd reg 13v 19v p on pgnd figure 2. max782 block diagram downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 11 shoot- through control r q 60khz lpf minimum current (idle-mode) 25mv r q level shift 1 s single-shot 1x main pwm comparator osc level shift current limit vl 30r 1r 3.3v 4 a synchronous rectifier control 0mv-100mv ref, 3.3v (or internal 5v reference) ss_ on_ 100mv vdd reg (see fig. 2) cs_ fb_ bst_ dh_ lx_ vl dl_ pgnd s s slope comp n n n figure 3. pwm controller block diagram downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 12 ______________________________________________________________________________________ +3 .3 v a nd +5 v pwm buc k cont rolle rs the two current-mode pwm controllers are identical except for different preset output voltages and the addition of a flyback winding control loop to the + 5v side (see figure 3, +3.3v/+5v pwm controller block diagram). each pwm is independent except for being synchronized to a master oscillator and sharing a c om- mon reference (ref) and logic supply (vl). each pwm can be turned on and off separately via on3 and on5 . the pwms are a direct-summing type, lacking a tradi - tional integrator-type error amplifier and the phas e shift associated with it. they therefore do not require a ny external feedback compensation components if the fi l- ter capacitor esr guidelines given in the design procedure are followed. the main gain block is an open-loop comparator that sums four input signals: an output voltage error s ignal, current-sense signal, slope-compensation ramp, and precision voltage reference. this direct-summing method approaches the ideal of cycle-by-cycle contr ol of the output voltage. under heavy loads, the contr oller operates in full pwm mode. every pulse from the osc il- lator sets the output latch and turns on the high-s ide switch for a period determined by the duty cycle (approximately v out /v in ). as the high-side switch turns off, the synchronous rectifier latch is set and, 60 ns later, the low-side switch turns on (and stays on until th e beginning of the next clock cycle, in continuous mo de, or until the inductor current crosses through zero, in discontinuous mode). under fault conditions where t he inductor current exceeds the 100mv current-limit threshold, the high-side latch is reset and the hig h-side switch is turned off. at light loads, the inductor current fails to excee d the 25mv threshold set by the minimum current compara- tor. when this occurs, the pwm goes into idle-mode, skipping most of the oscillator pulses in order to reduce the switching frequency and cut back switching loss es. the oscillator is effectively gated off at light lo ads because the minimum current comparator immediately resets the high-side latch at the beginning of each cycle, unless the fb_ signal falls below the refere nce voltage level. a flyback winding controller regulates the +15v vdd supply in the absence of a load on the main +5v out - put. if vdd falls below the preset +13v vdd regulat ion threshold, a 1s one-shot is triggered that extends the on-time of the low-side switch beyond the point whe re the inductor current crosses zero (in discontinuous mode). this causes inductor (primary) current to reverse, pulling current out of the output filter c apacitor and causing the flyback transformer to operate in t he forward mode. the low impedance presented by the transformer secondary in forward mode allows the +15v filter capacitor to be quickly charged again, bringing vdd into regulation. soft-start/ss_ inputs connecting capacitors to ss3 and ss5 allows gradual build-up of the +3.3v and +5v supplies after on3 an d on5 are driven high. when on3 or on5 is low, the appropriate ss capacitors are discharged to gnd. when on3 or on5 is driven high, a 4a constant cur- rent source charges these capacitors up to 4v. the resulting ramp voltage on the ss_ pins linearly inc reas- es the current-limit comparator setpoint so as to increase the duty cycle to the external power mosfe ts up to the maximum output. with no ss capacitors, t he circuit will reach maximum current limit within 10 s. soft-start greatly reduces initial in-rush current peaks and allows start-up time to be programmed externall y. synchronous rectifiers synchronous rectification allows for high efficienc y by reducing the losses associated with the schottky re cti- fiers. also, the synchronous rectifier mosfets are necessary for correct operation of the max782's boo st gate-drive and vdd supplies. when the external power mosfet n1 (or n2) turns off , energy stored in the inductor causes its terminal v olt- age to reverse instantly. current flows in the loo p formed by the inductor, schottky diode, and load, a n action that charges up the filter capacitor. the sc hottky diode has a forward voltage of about 0.5v which, although small, represents a significant power loss , degrading efficiency. a synchronous rectifier, n3 (or n4), parallels the diode and is turned on by dl3 (o r dl5) shortly after the diode conducts. since the o n resistance (r ds(on) ) of the synchronous rectifier is very low, the losses are reduced. the synchronous rectifier mosfet is turned off when the inductor current falls to zero. cross conduction (or shoot-through) is said to oc cur if the high-side switch turns on at the same time a s the synchronous rectifier. the max782s internal break - before-make timing ensures that shoot-through does not occur. the schottky rectifier conducts during the t ime that neither mosfet is on, which improves efficienc y by preventing the synchronous-rectifier mosfets lossy body diode from conducting. the synchronous rectifier works under all operating condi- tions, including discontinuous-conduction and idle- mode. the +5v synchronous rectifier also controls the 15v vdd voltage (see the high-side supply (vdd) section). downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 13 boost gate-driver supply gate-drive voltage for the high-side n-channel swit ch is generated with a flying-capacitor boost circuit as shown in figure 4. the capacitor is alternately charged f rom the vl supply via the diode and placed in parallel with the high-side mosfets gate-source terminals. on st art- up, the synchronous rectifier (low-side) mosfet for ces lx_ to 0v and charges the bst_ capacitor to 5v. on the second half-cycle, the pwm turns on the high-side mosfet by connecting the capacitor to the mosfet gate by closing an internal switch between bst_ and dh_. this provides the necessary enhancement voltag e to turn on the high-side switch, an action that bo osts the 5v gate-drive signal above the battery voltage. ringing seen at the high-side mosfet gates (dh3 and dh5) in discontinuous-conduction mode (light loads) is a natural operating condition caused by the residua l energy in the tank circuit formed by the inductor a nd stray capacitance at the lx_ nodes. the gate driver negative rail is referred to lx_, so any ringing th ere is directly coupled to the gate-drive supply. modes of operation pwm mode under heavy loads C over approximately 25% of full load C the +3.3v and +5v supplies operate as continuous- cur- rent pwm supplies (see typical operating characteristics ). the duty cycle (%on) is approximately: %on = v out /v in current flows continuously in the inductor: first, it ramps up when the power mosfet conducts; then, it ramps down during the flyback portion of each cycle as energy is put into the inductor and then dis- charged into the load. note that the current flowi ng into the inductor when it is being charged is also flowing into the load, so the load is continuously receiving current from the inductor. this minimize s output ripple and maximizes inductor use, allowing very small physical and electrical sizes. output r ip- ple is primarily a function of the filter capacitor (c7 or c6) effective series resistance (esr) and is typica lly under 50mv (see the design procedure section). output ripple is worst at light load and maximum input voltage. idle mode under light loads (<25% of full load), efficiency i s fur- ther enhanced by turning the drive voltage on and o ff for only a single clock period, skipping most of th e clock pulses entirely. asynchronous switching, see n as ghosting on an oscilloscope, is thus a normal ope rating condition whenever the load current is less than approximately 25% of full load. at certain input voltage and load conditions, a tra nsition region exists where the controller can pass back an d forth from idle-mode to pwm mode. in this situatio n, short bursts of pulses occur that make the current waveform look erratic, but do not materially affect the output ripple. efficiency remains high. current limiting the voltage between cs3 (cs5) and fb3 (fb5) is cont in- uously monitored. an external, low-value shunt res istor is connected between these pins, in series with the in duc- tor, allowing the inductor current to be continuous ly mea- sured throughout the switching cycle. whenever thi s voltage exceeds 100mv, the drive voltage to the ext ernal high-side mosfet is cut off. this protects the mos fet, the load, and the battery in case of short circuits or tem- porary load surges. the current-limiting resistor r1 (r2) is typically 25m (20m ) for 3a load current. oscillator frequency; sync input the sync input controls the oscillator frequency. connecting sync to gnd or to vl selects 200khz oper a- tion; connecting to ref selects 300khz operation. sync can also be driven with an external 240khz to 350kh z cmos/ttl source to synchronize the internal oscilla tor. normally, 300khz is used to minimize the inductor a nd filter capacitor sizes, but 200khz may be necessary for low input voltages (see low-voltage (6-cell) operation ). level translator pwm vl bst_ dh_ lx_ dl_ vl battery input vl figure 4. boost supply for gate drivers downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 14 ______________________________________________________________________________________ h igh-side supply (v dd) the 15v vdd supply is obtained from the rectified a nd filtered secondary of transformer l2. vdd is enabl ed whenever the +5v supply is on (on5 = high). the pr i- mary and secondary of l2 are connected so that, dur - ing the flyback portion of each cycle (when mosfet n2 is off and n4 is on), energy stored in the core is transferred into the +5v load through the primary a nd into vdd through the secondary, as determined by th e turns ratio. the secondary voltage is added to the +5v to make vdd. see the typical operating characteristics for the vdd supplys load capability. unlike other coupled-inductor flyback converters, t he vdd voltage is regulated regardless of the loading on the +5v output. (most coupled-inductor converters can only support the auxiliary output when the main out put is loaded.) when the +5v supply is lightly loaded, the circuit achieves good control of vdd by pulsing the mosfet normally used as the synchronous rectifier. this draws energy from the +5v supplys output capa c- itor and uses the transformer in a forward-converte r mode (i.e., the +15v output takes energy out of the secondary when current is flowing in the primary). note that these forward-converter pulses are inter- spersed with normal synchronous-rectifier pulses, a nd they only occur at light loads on the +5v rail. the transformer secondarys rectified and filtered out- put is only roughly regulated, and may be between 1 3v and 19v. it is brought back into vdd, which is als o the feedback input, and used as the source for the pcmc ia vpp regulators (see generating additional vpp outputs using external linear regulators ). it can also be used as the vh power supply for the comparators or any external mosfet drivers. when the input voltage is above 20v, or when the +5 v supply is heavily loaded and vdd is lightly loaded, l2s interwinding capacitance and leakage inductance can produce voltages above that calculated from the tur ns ratio. a 3ma shunt regulator limits vdd to 19v. clock-frequency noise on the vdd rail of up to 3vp- p is a facet of normal operation, and can be reduced by adding more output capacitance. pcm ci a-com pa t ible progra m m a ble v pp supplie s two independent regulators are provided to furnish pcmcia vpp supplies. the vppa and vppb outputs can be programmed to deliver 0v, 5v, 12v, or to be high impedance. the 0v output mode has a 250 pull-down to discharge external filter capacitors and ensure that flash eproms cannot be accidentally programmed. these linear regulators operate from the high-side sup- ply (vdd), and each can furnish up to 60ma. bypass vppa and vppb to gnd with at least 1f, with the bypass capacitors less than 20mm from the vpp pins. the outputs are programmed with da0, da1, db0 and db1, as shown in table 2. these codes are intel 82365 (pcmcia digital control ler) compatible. for other interfaces, one of the input s can be permanently wired high or low and the other togg led to turn the supply on and off. the truth table sho ws that either a 0 or 1 can be used to turn each supply on. the high-impedance state is to accomodate external programming voltages. the two vpp outputs can be safely connected in parallel for increased load cap ability if the control inputs are also tied together (i.e., da0 to db0, da1 to db1). if vpaa and vppb are connected in parallel, some devices may exhibit several milliamp s of increased quiescent supply current when enabled, du e to slightly mismatched output voltage set points. com pa ra t ors three noninverting comparators can be used as preci - sion voltage comparators or high-side drivers. the supply for these comparators (vh) is brought out an d may be connected to any voltage between +3v and +19v. the noninverting inputs (d1-d3) are high imp ed- ance, and the inverting input is internally connect ed to a 1.650v reference. each output (q1-q3) sources 20a from vh when its input is above 1.650v, and sinks 500a to gnd when its input is below 1.650v. the q1-q3 outputs can be fixed together in wired-or configuration since the pull-up current is only 20 a. connecting vh to a logic supply (5v or 3v) allows t he comparators to be used as low-battery detectors. f or dri- ving n-channel power mosfets to turn external loads on and off, vh should be 6v to 12v higher than the loa d volt- age. this enables the mosfets to be fully turned o n and results in low r ds(on) . vdd is a convenient source for vh. da0 da1 vppa 0 1 0 1 0v 5v 12v hi-z 0 0 1 1 db0 db1 vppb 0 0 1 1 0 1 0 1 0v 5v 12v hi-z table 2. vpp program codes downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 15 the comparators are always active when v+ is above +4v, even when vh is 0v. thus, q1-q3 will sink cur rent to gnd even when vh is 0v, but they will only sourc e current from vh when vh is above approximately 1.5v . if q1, q2, or q3 is externally pulled above vh, an inter- nal diode conducts, pulling vh a diode drop below t he output and powering anything connected to vh. this voltage will also power the other comparator output s. i nt e rna l v l a nd ref supplie s an internal linear regulator produces the 5v used b y the internal control circuits. this regulators output is avail- able on pin vl and can source 5ma for external load s. bypass vl to gnd with 4.7f. to save power, when the +5v switch-mode supply is above 4.5v, the inter nal linear regulator is turned off and the high-efficie ncy +5v switch-mode supply output is connected to vl. the internal 3.3v bandgap reference (ref) is powere d by the internal 5v vl supply, and is always on. it can furnish up to 5ma. bypass ref to gnd with 0.22f, plus 1f/ma of load current. both the vl and ref outputs remain active, even whe n the switching regulators are turned off, to supply mem- ory keep-alive power. these linear-regulator ouputs can be directly conne cted to the corresponding step-down regulator outputs (i .e., ref to +3.3v, vl to +5v) to keep the main supplies alive in standby mode. however, to ensure start-up, stan dby load currents must not exceed 5ma on each supply. fault protection the +3.3v and +5v pwm supplies, the high-side sup- ply, and the comparators are disabled when either o f two faults is present: vl < +4.0v or ref < +2.8v (8 5% of its nominal value). __________________de sign proc e dure figure 1s schematic and table 2s component list show values suitable for a 3a, +5v supply and a 3a, +3.3v supply. this circuit operates with input vol tages from 6.5v to 30v, and maintains high efficiency wit h output currents between 5ma and 3a (see the typical operating characteristics ). this circuits components may be changed if the design guidelines described i n this section are used C but before beginning the des ign, the following information should be firmly establis hed: v in(max) , the maximum input (battery) voltage. this value should include the worst-case conditions unde r which the power supply is expected to function, suc h as no-load (standby) operation when a battery charg er is connected but no battery is installed. v in(max) can- not exceed 30v. v in(min) , the minimum input (battery) voltage. this value should be taken at the full-load operating cu r- rent under the lowest battery conditions. if v in(min) is below about 6.5v, the power available from the vdd supply will be reduced. in addition, the filte r capacitance required to maintain good ac load reg- ulation increases, and the current limit for the +5 v supply has to be increased for the same load level. +3 .3 v i nduc t or (l1 ) three inductor parameters are required: the induct ance value (l), the peak inductor current (i lpeak ), and the coil resistance (r l ). the inductance is: v out x (v in(max) - v out ) l = - v in(max) x f x i out x lir where: v out = output voltage, 3.3v; v in(max) = maximum input voltage (v); f = switching frequency, normally 300khz; i out = maximum +3.3v dc load current (a); lir = ratio of inductor peak-to-peak ac current to average dc load current, typically 0.3. a higher value of lir allows smaller inductance, bu t results in higher losses and higher ripple. the highest peak inductor current (i lpeak ) equals the dc load current (i out ) plus half the peak-to-peak ac inductor current (i lpp ). the peak-to-peak ac inductor current is typically chosen as 30% of the maximum d c load current, so the peak inductor current is 1.15 times i out . the peak inductor current at full load is given by: v out x (v in(max) - v out ) i lpeak = i out + . 2 x f x l x v in(max) the coil resistance should be as low as possible, preferably in the low milliohms. the coil is effec tively in series with the load at all times, so the wire loss es alone are approximately: power loss = i out 2 x r l in general, select a standard inductor that meets t he l, i lpeak , and r l requirements (see tables 3 and 4). if a standard inductor is unavailable, choose a core wit h an li 2 parameter greater than l x i lpeak 2 , and use the largest wire that will fit the core. downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 16 ______________________________________________________________________________________ +5 v t ra nsform e r (t 1 ) table 3 lists two commercially available transforme rs and parts for a custom transformer. the following instructions show how to determine the transformer parameters required for a custom design: l p , the primary inductance value i lpeak , the peak primary current li 2 , the cores energy rating r p and r s , the primary and secondary resistances n, the primary-to-secondary turns ratio. the transformer primary is specified just as the +3 .3v inductor, using v out = +5.0v; but the secondary output (vdd) power must be added in as if it were part of the primary. vdd current (i dd ) usually includes the vppa and vppb output currents. the total +5v power, p total , is the sum of these powers: p total = p5 + p dd where: p5 = v out x i out ; p dd = vdd x i dd ; and: v out = output voltage, 5v; i out = maximum +5v load current (a); vdd = vdd output voltage, 15v; i dd = maximum vdd load current (a); so: p total = (5v x i out ) + (15v x i dd ) and the equivalent +5v output current, i total , is: i total = p total / 5v = [(5v x i out ) + (15v x i dd )] / 5v. the primary inductance, l p , is given by: v out x (v in(max) - v out ) l p = v in(max) x f x i total x lir where: v out = output voltage, 5v; v in(max) = maximum input voltage; f = switching frequency, normally 300khz; i total = maximum equivalent load current (a); lir = ratio of primary peak-to-peak ac current to average dc load current, typically 0.3. the highest peak primary current (i lpeak ) equals the total dc load current (i total ) plus half the peak-to-peak ac primary current (i lpp ). the peak-to-peak ac primary current is typically chosen as 30% of the maximum d c load current, so the peak primary current is 1.15 t imes i total . a higher value of lir allows smaller inductance, but results in higher losses and higher ripple. the peak current in the primary at full load is giv en by: v out x (v in(max ) - v out ) i lpeak = i total + . 2 x f x l p x v in(max) choose a core with an li 2 parameter greater than l p x i lpeak 2 . the winding resistances, r p and r s , should be as low as possible, preferably in the low milliohms. use the largest gauge wire that will fit on the core. the coil is effectively in series with the load at all times, s o the resistive losses in the primary winding alone are approximately (i total ) 2 x r p . the minimum turns ratio, n min , is 5v:(15v-5v). use 1:2.2 to accommodate the tolerance of the +5v supply. a greater ratio will reduce efficiency of the vpp reg ulators. minimize the diode capacitance and the interwinding capacitance, since they create losses through the vdd shunt regulator. these are most significant wh en the input voltage is high, the +5v load is heavy, a nd there is no load on vdd. ensure the transformer secondary is connected with the right polarity: a vdd supply will be generated wit h either polarity, but proper operation is possible only wit h the cor- rect polarity. test for correct connection by meas uring the vdd voltage when vdd is unloaded and the input volt age (v in ) is varied over its full range. correct connectio n is indicated if vdd is maintained between 13v and 20v. current-sense resistors (r1, r2) the sense resistors must carry the peak current in the inductor, which exceeds the full dc load current. the internal current limiting starts when the volta ge across the sense resistors exceeds 100mv nominally, 80mv minimum. use the minimum value to ensure adequate output current capability: for the +3.3v supply, r1 = 80mv / (1.15 x i out ); for the +5v supply, r2 = 80mv/(1.15 x i total ), assuming that lir = 0.3. since the sense resistance values (e.g. r1 = 25m for i out = 3a) are similar to a few centimeters of narrow traces on a printed circuit board, trace resistance can contribute significant errors. to prevent this, ke lvin connect the cs_ and fb_ pins to the sense resistors ; i.e., use separate traces not carrying any of the i nduc- tor or load current, as shown in figure 5. run these traces parallel at minimum spacing from o ne another. the wiring layout for these traces is cri tical for stable, low-ripple outputs (see the layout and grounding section). m osfet sw it c he s (n 1 -n 4 ) the four n-channel power mosfets are usually iden- tical and must be logic-level fets; that is, they must be fully on (have low r ds(on) ) with only 4v gate- source drive voltage. the mosfet r ds(on) should ideally be about twice the value of the sense resis tor. mosfets with even lower r ds(on) have higher gate capacitance, which increases switching time and transition losses. downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 17 mosfets with low gate-threshold voltage specifica- tions (i.e., maximum v gs(th) = 2v rather than 3v) are preferred, especially for high-current (5a) applica tions. out put filt e r ca pa c it ors (c6 , c7 , c1 4 ) the output filter capacitors determine the loop sta bility and output ripple voltage. to ensure stability, th e mini- mum capacitance and maximum esr values are: v ref c f > v out x r cs x 2 x x gbwp and, v out x r cs esr cf < v ref where: c f = output filter capacitance, c6 or c7 (f); v ref = reference voltage, 3.3v; v out = output voltage, 3.3v or 5v; r cs = sense resistor ( ); gbwp = gain-bandwidth product, 60khz; esr cf = output filter capacitor esr ( ). be sure to select output capacitors that satisfy both the minimum capacitance and maximum esr require- ments. to achieve the low esr required, it may be appropriate to use a capacitance value 2 or 3 times larger than the calculated minimum. the output ripple in continuous-current mode is: v out(rpl) = i lpp(max) x (esr cf +1/(2 x x f x c f )). in idle-mode, the ripple has a capacitive and resis tive component: 4 x 10 -4 x l v out(rpl) (c) = x r cs 2 x c f 1 1 ( + ) volts v out v in - v out 0.02 x esr cf v out(rpl) (r) = - volts r cs the total ripple, v out(rpl) , can be approximated as fol- lows: if v out(rpl) (r) < 0.5 v out(rpl) (c), then v out(rpl) = v out(rpl) (c), otherwise, v out(rpl) = 0.5 v out(rpl) (c) + v out(rpl) (r). diode d2 the voltage rating of d2 should be at least 2 x v in + 5v plus a safety margin. a rating of at least 75v is necessary for the maximum 30v supply. a schottky diode is preferable for lower input voltages, and i s required for input voltages under 7v. use a high- speed silicon diode (with a higher breakdown voltag e and lower capacitance) for high input voltages. d2 s current rating should exceed twice the maximum cur- rent load on vdd. diode s d3 a nd d4 use 1n5819s or similar schottky diodes. d3 and d4 conduct only about 3% of the time, so the 1n5819s 1a current rating is conservative. the voltage rat ing of d3 and d4 must exceed the maximum input supply voltage from the battery. these diodes must be schottky diodes to prevent the lossy mosfet body diodes from turning on, and they must be placed physically close to their associated synchronous re cti- fier mosfets. soft -st a rt ca pa c it ors (c8 , c9 ) a capacitor connected from gnd to either ss pin cau s- es that supply to ramp up slowly. the ramp time to full current limit, t ss , is approximately 1ms for every nf of capacitance on ss_, with a minimum value of 10s. typical capacitor values are in the 10nf to 100nf range; a 5v rating is sufficient. max782 kelvin sense traces sense resistor main current path fat, high-current traces figure 5. kelvin connections for the current-sense resistors downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 18 ______________________________________________________________________________________ because this ramp is applied to the current-limit c ircuit, the actual time for the output voltage to ramp up depends on the load current and output capacitor value. using figure 1s circuit with a 2a load and no ss capacitor, full output voltage is reached about 600s after on_ is driven high. boost ca pa c it ors (c4 , c5 ) capacitors c4 and c5 store the boost voltage and pr o- vide the supply for the dh3 and dh5 drivers. use 0 .1f and place each within 10mm of the bst_ and lx_ pins . boost diode s (d1 a, d1 b) use high-speed signal diodes; e.g., 1n4148 or equiv alent. bypa ss ca pa c it ors input filter capacitors (c1, c13) use at least 3f/w of output power for the input fi lter capacitors, c1 and c13. they should have less than 150m esr, and should be located no further than 10mm from n1 and n2 to prevent ringing. connect the negative terminals directly to pgnd. do not exceed the surge current ratings of input bypass capacitors. vpp and vdd bypass capacitors (c10, c11, c12) use 2.2f for vdd, and 1f for vppa and vppb. table 3. surface-mount components (see figure 1 for schematic diagram and table 4 for phone numbers.) ec11fs1 nihon fast-recovery high voltage diode d2 sprague sprague sprague sprague murata-erie 1n4148smtn diodes (fast recovery) 33f, 35v tantalum capacitors lr2010-01-r020-f irc 0.020 , 1% (smt) resistor r2 lr2010-01-r025-f irc 0.025 , 1% (smt) resistor r1 si9410dy siliconix n-channel mosfets (so-8) n1-n4 cdr125-100 sumida 10h, 2.65a inductor l1 ec10qs04 nihon 1n5819 smt diodes d3, d4 baw56 philips d1a, d1b 595dd225x0025b2b 2.2f, 25v tantalum capacitor c12 595dd105x0035a2b 1f, 35v tantalum capacitors c10, c11 grm42-6x7r103k50v murata-erie 0.01f, 16v ceramic capacitors c8, c9 595d157x0010d2b sprague 150f, 10v tantalum capacitors c7, c14 595d337x0010r2b sprague 330f, 10v tantalum capacitor c6 grm42-6x7r104k50v 0.1f, 16v ceramic capacitors c4, c5 595d475x0016a2b 1f, 20v tantalum capacitor c3 595d475x0016a2b 4.7f, 16v tantalum capacitor c2 595d336x0035r2b sprague c1, c13 part no. manufacturer specification component coiltronics transpower technologies transformer (for 5.5v, 200khz operation) pc40eem12.7/13.7-a160 bem12.7/13.7-118g fem12.7/13.7-a 8 turns #24 awg 18 turns #26 awg tdk tdk tdk custom transformer: core set bobbin clamp primary secondary l2 ctx03-12062-1 coiltronics ctx03-12067-1 tti5870 transformer (these two have different sizes and pinouts) downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 19 __________applic a t ions i nform a t ion effic ie nc y conside ra t ions achieving outstanding efficiency over a wide range of loads is a result of balanced design rather than br ute- force overkill, particularly with regard to selecti ng the power mosfets. generally, the best approach is to design for two loading conditions, light load and h eavy load (corresponding to suspend and run modes in the host computer), at some nominal battery voltage (su ch as 1.2v/cell for nicd or nimh). efficiency improve s as the input voltage is reduced, as long as the high-s ide switch saturation voltage is low relative to the in put volt- age. if there is a choice, use the lowest-voltage battery pack possible, but with at least six cells. heavy-load efficiency losses due to parasitic resistances in the switches , coil, and sense resistor dominate at high load-curr ent levels. under heavy loads, the max782 operates in the continuous-conduction mode, where there is a large dc offset to the inductor current plus a small sawt ooth ac component (see the +3.3v inductor section). this dc current is exactly equal to the load current C a fact that makes it easy to estimate resistive losses thr ough the assumption that total inductor current is equal to this dc offset current. the major loss mechanisms under heavy loads are, in usual order of importance: i 2 r losses gate-charge losses diode-conduction losses transition losses capacitor-esr losses losses due to the operating supply current of the i c. inductor core losses are fairly low at heavy loads because the inductor currents ac component is smal l. therefore, they are not accounted for in this analy sis. efficiency = p out /p in x 100% = p out /(p out + pd total ) x 100% pd total = pd (i 2 r) + pd gate + pd diode + pd tran + pd cap + pd ic pd (i 2 r) = resistive loss = (i load 2 ) x (r coil + r ds(on) + r cs ) where r coil is the dc resistance of the coil, r ds(on) is the drain-source on resistance of the mosfet, and r cs is the current-sense resistor value. note that the r ds(on) term assumes that identical mosfets are employed for both the synchronous rectifier and hig h- side switch, because they time-share the inductor c ur- rent. if the mosfets are not identical, losses can be estimated by averaging the two individual r ds(on) terms according to duty factor. pd gate = gate driver loss = q g x f x vl where vl is the max782s logic supply voltage (nomi - nally 5v) and q g is sum of the gate charge for low- side and high-side switches. note that gate charge losses are dissipated in the ic, not the mosfets, and therefore contribute to package temperature ris e. for matched mosfets, q g is simply twice the gate charge of a single mosfet (a data sheet specifica- tion). if the +5v buck smps is turned off, replace vl in this equation with v in . p diode = diode conduction losses = i load x v d x t d x f where t d is the diodes conduction time (typically 110ns), v d is the forward voltage of the schottky diode, and f is the switching frequency. v in 2 x c rss x i load x f pd tran = transition loss = i drive company usa phone central semi coiltronics irc murata-erie nihon siliconix sprague sumida tdk transpower tech. factory fax [country code] table 4. surface-mount components (516) 435-1110 (407) 241-7876 (512) 992-7900 (404) 736-1300 (805) 867-2555 (408) 988-8000 (603) 224-1961 (708) 956-0666 (708) 803-6100 (702) 831-0140 [ 1] (516) 435-1824 [ 1] (407) 241-9339 [ 1] (213) 772-9028 [ 1] 404 736-3030 [81] 3-3494-7414 [ 1] (408) 727-5414 [ 1] (603) 224-1430 [81] 3-3607-5144 [81] 3-3278-5358 [ 1] 702 831-3521 downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 20 ______________________________________________________________________________________ where c rss is the reverse transfer capacitance of the high-side mosfet (a data sheet parameter), f is the switching frequency, and i drive is the peak current available from the max782s large high-side gate dr i- ver outputs (dh5 or dh3, approximately 1a). additional switching losses are introduced by other sources of stray capacitance at the switching node, including the catch diode capacitance, coil interwi nd- ing capacitance, and low-side switch-drain capaci- tance. they are given as pd sw = v in 2 x c stray x f, but are usually negligible compared to c rss losses. the low-side switch introduces only tiny switching losses, since its drain-source voltage is already l ow when it turns on. pd cap = capacitor esr loss = i rms 2 x esr and, i rms = rms ac input current v out (v in - v out ) = i load x v in where esr is the equivalent series resistance of th e input bypass capacitor. note that losses in the ou tput filter capacitors are small when the circuit is hea vily loaded, because the current into the capacitor is n ot chopped. the output capacitor sees only the small ac sawtooth ripple current. ensure that the input byp ass capacitor has a ripple current rating that exceeds the value of i rms . pd ic is the ics quiescent power dissipation and is a da ta sheet parameter (6mw typically for the entire ic at v in = 15v). this power dissipation is almost completely inde- pendent of supply voltage whenever the +5v step-dow n switch-mode power supply is on, since power to the chip is bootstrapped from the +5v output. when calculat ing the efficiency of each individual buck controller, use 3mw for pd ic , since each controller consumes approximately half of the total quiescent supply current. example: +5v buck smps at 300khz, v in = 15v, i load = 2a, r cs = r coil = esr = 25m , both transistors are si9410dy with r ds(on) = 0.05 , c rss = 160pf, and q g = 30nc. pd total = 400mw (i 2 r) + 90mw (gate) + 36mw (diode) + 22mw (tran) + 22mw (cap) + 3mw (ic) = 573mw efficiency = 10w/(10w + 573mw) x 100% = 94.6% (actual measured value = 94%). light-load efficiency under light loads, the pwms operate in the disconti nu- ous-conduction mode, where the inductor current dis - charges to zero at some point during each switching cycle. new loss mechanisms, insignificant at heavy loads, start to become important. the basic differ ence is that, in discontinuous mode, the inductor curren ts ac component is large compared to the load current. this increases core losses and losses in the output fil- ter capacitors. ferrite cores are recommended over powdered toroid types for best light-load efficienc y. at light loads, the inductor delivers triangular cu rrent pulses rather than the nearly constant current foun d in continuous mode. these pulses ramp up to a point s et by the idle-mode current comparator, which is inter nally fixed at approximately 25% of the full-scale curren t-limit level. this 25% threshold provides an optimum bal- ance between low-current efficiency and output volt age noise (the efficiency curve would actually look bet ter if this threshold were set at about 45%, but the outpu t noise would then be too high). reducing i 2 r losses though the brute-force method of specifying huge, low-r ds(on) mosfets can result in atrocious efficiency, especially at mid-range and l ight- load conditions. even at heavy loads, the gate cha rge losses introduced by huge 50a mosfets usually more than offset any gain obtained through lower r ds(on) . la yout a nd grounding good layout is necessary to achieve the designed ou t- put power, high efficiency, and low noise. good la yout includes use of a ground plane, appropriate compo- nent placement, and correct routing of traces using appropriate trace widths. the following points are in order of importance: 1. a ground plane is essential for optimum performan ce. in most applications, the power supply is located o n a multilayer motherboard, and full use of the four or more copper layers is recommended. use the top and bottom layers for interconnections, and the inn er layers for an uninterrupted ground plane. 2. keep the kelvin-connected current-sense traces short, close together, and away from switching nodes. see figure 5. 3. place the lx node components n1, n3, d3, and l1 as close together as possible. this reduces resisti ve and switching losses and keeps noise due to ground inductance confined. do the same with the other lx node components n2, n4, d4, and l2. 4. the input filter capacitor c1 should be less than 10mm away from n1s drain. the connecting cop- per trace carries large currents and must be at lea st 2mm wide, preferably 5mm. similarly, place c13 close to n2s drain, and con- nect them with a wide trace. downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 21 5. keep the gate connections to the mosfets short fo r low inductance (less than 20mm long and more than 0.5mm wide) to ensure clean switching. 6. to achieve good shielding, it is best to keep all high-voltage switching signals (mosfet gate dri- ves dh3 and dh5, bst3 and bst5, and the two lx nodes) on one side of the board and all sensitive nodes (cs3, cs5, fb3, fb5 and ref) on the other side. 7. connect the gnd and pgnd pins directly to the ground plane, which should ideally be an inner laye r of a multilayer board. 8. connect the bypass capacitor c2 very close (less than 10mm) to the vl pin. 9. minimize the capacitance at the transformer sec- ondary. place d5 and c12 very close to each other and to the secondary, then route the output to the ics vdd pin with a short trace. bypass with 0.1f clos e to the vdd pin if this trace is longer than 50mm. the layout for the evaluation board is shown in the evaluation kit section. it provides an effective, low- noise, high-efficiency example. pow e r-re a dy a nd pow e r se que nc ing a power-ready signal can be generated from one of the comparator outputs by connecting one of the sup - plies (e.g., the +5v output C see figure 6) through a high-resistance voltage divider to the comparator i nput. the threshold for the +5v-output comparator is set by r1 and r2 according to the formula: v th = 1.65v x (r1 + r2) / r2. for example, choosing r1 = 1m and r2 = 604k sets the nominal threshold to 4.38v. if the power-ready signal is required to indicate w hen both the +3.3v and the +5v supplies have come up, use the max707 supervisory circuit shown in figure 7. the threshold for the +3.3v-line comparator is set by r1 and r2 according to the formula: v th = 1.25v x (r1 + r2) / r2. for example, choosing r1 = 1.2m and r2 = 1m sets the nominal threshold to 2.75v. the thresh- old for the +5v supply is preset inside the max707, and is typically 4.65v. the reset outputs remain a ssert- ed while either supply line is below its threshold, and for at least 140ms after both lines are fully up. if sequencing of the +3.3v and +5v supplies is crit ical, several approaches are possible. for example, the ss3 and ss5 capacitors can be sized to ensure that the two supplies come up in the desired order. thi s technique requires that the ss capacitors be select ed specifically for each individual situation, because the loading on each supply affects its power-up speed. another approach uses the power-ready comparator output signal (see figure 6) from one supply as a c on- trol input to the on_ pin of the other supply. max782 1m 604k r1 r2 d_ gnd 1.65v q_ fb5 +5v power-ready +5v supply figure 6. power-ready signal for the +5v supply reset max707 +5v supply +3.3v supply r1 1.24m r2 1m power ready power ready pfi 1.25v gnd 4.65v pfo mr reset reset v cc figure 7. power-ready signal covers both +3.3v and +5v supplies with external voltage monitor ic (max707) downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 22 ______________________________________________________________________________________ figure 8 shows a more complex example of power sequencing. on power-up, the intel 486sl computer requires the +5v supply to come up before the +3.3v supply. a power-ready signal is required 50ms later. this circuits on3 output connects to the max782s on3 pin, and can be wire-or connected with an open- drain output to enable another circuit to turn the +3.3v supply off. pcm ci a slot +3 .3 v /+5 v v cc sw it c hing the max782 contains level shifters that simplify dr iving external power mosfets to switch pcmcia card vcc to 3.3v and 5v. while a pcmcia card is being inser ted into the socket, the vcc pins on the card edge shou ld be powered down to 0v so hot insertion does not damage the pcmcia card. the simplest way to do thi s is to use a mechanical switch that has to be physic ally opened before the pcmcia card can be inserted. the switch, which disconnects vcc, can be closed only when the card has been fitted snugly into its socke t. figure 9s circuit illustrates this approach and co rrectly shows the connections to both mosfets: n2 appears to be inserted with drain and source the wrong way around, but this is necessary to prevent its body d iode from pulling the +3.3v supply up to 5v when vcc is connected to the +5v supply. figure 10s circuit provides an alternative method of connecting the vcc supply to the pcmcia slot. whil e it avoids using a mechanical switch, it does not pr ovide the security of a physical interlock. placing the two mosfets n1 and n2 with their body diodes facing in opposite directions allows vcc to be shut down to 0 v without using a mechanical switch, and allows vcc t o be driven to 5v without the +3.3v supply being pull ed up to 5v. p n hyst1 c4 100nf vcc r3 1m r6 1m c3 100nf power ready on3 c1 22nf out2 r2 390k r1 1m r4 1m r5 820k c2 100 nf +5v supply +3.3v supply set1 set2 gnd 1.3v icl7665 figure 8. power-up sequencing for the intel 486sl pcmcia 2.0 digital controller vcc_en0 vcc_en1 fb5 fb3 q2 d1 d2 vdd vh +5v supply mechanical switch slot vcc +3.3v supply max782 d s g n2 q1 d s g n1 note: mosfet body diodes shown for clarity. figure 9. simple switching for pcmcia slot vcc pcmcia 2.0 digital controller vcc_en0 vcc_en1 fb5 fb3 q2 d1 d2 +5v +3.3v max782 n2 q1 n3 n1 vdd vh 100 f slot vcc note: mosfet body diodes shown for clarity. figure 10. using the level shifters to switch pcmci a slot vcc downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 23 the max782 has three comparators/level-shifters tha t can be used for this purpose, and two that are need ed for each pcmcia port. two transistors can be used as shown in figure 11 to provide two additional ttl-in put mosfet gate drivers for a second pcmcia slot. the component values have been carefully chosen to prov ide smooth switching from 5v to 3.3v without make-befor e- break glitches, and without a break in the vcc supp ly. low -v olt a ge (6 -ce ll) ope ra t ion low input voltages, such as the 6v end-of-life volt age of a 6-cell nicd battery, place extra demands on the + 5v buck regulator because of the very low input-output dif- ferential voltage. the standard application circuit works well with supply voltages down to 6.5v; at input vo ltages less than 6.5v, some component changes are needed (see table 5), and the operating frequency must be set to 200khz. the two main issues are load-transient response and load capability of the +15v vdd supply . the +5v supplys load-transient response is impaire d due to reduced inductor-current slew rate, which is in turn caused by reduced voltage applied across the buck i nduc- tor during the high-side switch-on time. so, the +5 v output sags when hit with an abrupt load current change, u nless the +5v filter capacitor value is increased. note t hat only the capacitance is affected and esr requirements dont change. therefore, the added capacitance can be sup - plied by an additional low-cost bulk capacitor in p arallel with the normal low-esr switching-regulator capacitor. t he equation for voltage sag under a step-load change f ollows: i step 2 x l v sag = 2 x c f x (v in(min) x dmax - v out ) where dmax is the maximum duty cycle. higher duty cycles are possible when the oscillator frequency i s reduced to 200khz, due to fixed propagation delays through the pwm comparator becoming a lesser part o f the whole period. the tested worst-case limit for d max is 92% at 200khz. lower inductance values can reduc e the filter capacitance requirement, but only at the expense of increased noise at high input voltages ( due to higher peak currents). the components shown in table 5 allow the main +5v supply to deliver 2a from v in = 5.5v, or alternatively allow the +15v supply to deliver 70ma while simulta ne- ously providing +5v at 2a from v in = 5.7v. note: components for +3.3v dont need to be changed. the +15v supplys load capability is also affected by low input voltages, especially under heavy loads. w hen the +5v supply is heavily loaded, there simply isn t enough extra duty cycle left for the flyback windin g controller to deliver energy to the secondary. vdd load- current limitations are thus determined by the wors t- case duty-cycle limits, and also by any parasitic r esis- tance or inductance on the transformer secondary. these parasitics, most notably the transformer leak age inductance and the forward impedance of the +15v rectifier diode, limit the rate-of-rise of current in the sec- ondary during the brief interval when primary curre nt reverses and the transformer conducts in the forwar d mode. see the typical operating characteristics . for low-voltage applications that require heavy +15v lo ad currents (for example, 6-cell circuits where +12v v pp must deliver 120ma or more), see the max783 data sheet. this device is similar to the max782 except the +15v flyback winding controller has been shifted fr om the +5v side to the +3.3v side. table 5. components for low-voltage operation (circuit of figure 1, f = 200khz, v in range = 5.5v to 12v) transformer l2: filter capacitor c6: 660f flyback rectifier d2: 1n5819 or equivalent schottky diode coiltronics ctx03-12062 (low-leakage inductance, 10h primary) sense resistor: 25m pcmcia 2.0 digital controller vcc_en0 vcc_en1 max782 100 f slot vcc +5v vdd fb5 fb3 1m 1m +3.3v 1m 2n3904 2n3904 510k note: mosfet body diodes shown for clarity. figure 11. using discrete circuitry to switch pcmc ia 2.0 slot vcc downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 24 ______________________________________________________________________________________ t ot a l shut dow n circ uit s when the +5v and +3.3v supplies are off, the comple te max782 circuit consumes only about 70a, plus any leakage through the off mosfets. some nicd batter- ies can be damaged if they are fully discharged and then left for long periods (months) under load. ev en 100a can do damage if left long enough. the complete power-supply system can be shut down by taking on5 low, cutting the supply to the max782 s v+ pin, while the bootstrapped +5v supply is turned off. this removes the supply from the controller, and turns off all the supplies. in this condition, the current consumption drops to the level of the leakage curre nts in the off transistors. switching the v+ supply of f is easy because the v+ line draws very little power; switching the entire power input from the battery w ould be more difficult. figure 12 shows a logic interface for a momentary switch that toggles the whole system on and off. t he logic circuit runs from the battery supply, so the input voltage from the battery is limited to the normal o perat- ing range for the flip-flop gates, which is usually 18v for 4000-series cmos circuits. the active-high off inp ut permits the supplies to be turned off under logic c ontrol as well as when the switch is pushed. if this logi c input is not required, omit r1 and q1. the supplies can only be turned on using the hardware switch. for automa tic turn-off, connect the off input to a battery-voltag e sensing comparator or to a timer powered from vl. ensure that any signal connected to off does not glitch high at power-up. ge ne ra t ing addit iona l v pp out put s u sing ex t e rna l line a r re gula t ors figure 13 shows a low-dropout linear regulator designed to provide an additional vpp output from t he vdd line. it can be turned off with a logic-level signal; its output can be switched to 5v or 12v; and it pro - vides excellent rejection of the high-frequency noi se on vdd. if a monolithic linear regulator is used, choose one having good psrr performance at 300khz. zetex zvp2106g sot 223 v batt on/ off 1m 1 f r 1m cd4011b s 1m 1m r1 1m 1n4148 1 f off q1 2n4401 on5 1n4148 pgnd on on (+5.5v to +18v) 1n4148 on5 vl v+ 1m max782 1n4148 figure 12. hardware/software total shutdown circui t q2 2n7002 q1 2n4403 c1 100nf r4 1k c3 10nf r1 16.9k out c2 6.8 f r2 6.34k r3 26.7k q3 2n7002 12/5 off/on 6 4 3 2 7 r5 100k ref c4 10nf vdd u1 op27 off/on 12/5 v out (v) 1 x0 00 5 01 1 2 x = don't care from max782 from max782 figure 13. external regulator for additional vpp o utputs downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 25 ________eva lua t ion k it i nform a t ion the max782 evaluation kit (ev kit) is an assembled, surface-mount demonstration board. the kit embodie s the standard application circuit and uses dip switc hes to control the 3v, 5v, and vpp outputs. the board accepts battery input voltages between 6.5v and 30v , and provides up to 30w of output power. all functi ons are controlled by standard cmos/ttl logic levels. ___________ev k it quic k re fe re nc e to set up the ev kit, use the following procedure: 1. connect a power supply to the batt in terminals. the supply voltage should be between 6.5v and 30v. input current may be several amps, depending on the input voltage and the output power demanded. 2. turn on the +5v output by setting the on5 dip switch to on. the 5v out edge pad now supplies +5v at up to 3a, and +15v is now available at the +15v out edge pad. 3. turn on the +3.3v output by setting the on3 dip switch to on. the 3.3v out edge pad now sup- plies +3.3v at up to 3a. the two regulators may be operated independently. 4. to use the vppa/vppb programmable voltage out- puts, on5 must be enabled. set the four-circuit di p switch to the desired code and measure the output a t the vppa and vppb edge pads. da0 and da1 con- trol vppas state; db0 and db1 control vppbs state . _______ev k it de t a ile d de sc ript ion ba t t e ry i nput batt in C battery input, 6.5v to 30v gnd C ground the battery input voltage should be between 6.5v an d 30v. the input voltage upper limit is set by the v oltage rating of the input bypass capacitors, c1 and c13, and may not exceed the max782s 30v maximum rating. higher input voltages generally require physically larg- er input capacitors. low -ba t t e ry de t e c t ion com pa ra t ors to demonstrate the level shifters / high-side drive rs, on5 must be enabled so the +15v (vdd) is available to pull up the q1-q3 outputs. measure the high-sid e driver supply at the vh edge pad. logic-level edge pads d1-d3 control the outputs q1-q3. q1-q3 pull u p to vh whenever the corresponding input d1-d3 is at a logic-high level. when active, outputs q1-q3 pull up to vh. resistor r16, located on the back of the board, pulls the hi gh- side driver voltage vh up to +15v. by removing r16 and installing a resistor at the empty r15 site, vh may be tied to the +3.3v output. alternately, both r15 and r16 may be omitted and the user may supply an arbi- trary voltage between 3v and 20v at the vh edge pad . note that q1-q3 are not meant to drive high-current loads directly. the d1-d3 comparators can be used as precision volt - age detectors by installing resistor dividers at ea ch input (r11/r12, r10/r13, r9/r14). pow e r-supply cont rols on3 C enable 3.3v power supply on5 C enable 5.0v power supply sync C switch-mode power-supply frequency input (optional) v pp v olt a ge out put s the pcmcia-compatible programmable voltage out- puts are controlled by the da0, da1, db0, and db1 logic-level inputs. the max782 provides industry- standard intel 82365-comptaible vppa/vppb pcmcia controls (see pin description ). the four-circuit dip switch connects the same way as the edge pads. from left to right, switch 1 controls da1, switch 2 con- trols da0, switch 3 controls db1, and switch 4 cont rols db0. vppa and vppb are capable of supplying 60ma each. downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 26 ______________________________________________________________________________________ max782 x2d 15 da1 16 da0 17 db1 18 db0 d1 31 bst3 33 dh3 32 lx3 30 dl3 35 cs3 c5 0.1 f r3 1m r4 1m r5 1m r6 1m 34 fb3 1 on3 19 on5 x1a x1b 2 d1 3 d2 4 d3 r8 1m r7 1m r9 1m r10 1m r11 1m ss3 gnd pgnd ss5 36 12 26 20 r12 open r13 open r14 open d3b d2b d18 on3 on5 3.3v out x2c x2b x2a 5 vh 28 vl 9 vppa 11 vppb 10 vdd 24 bst5 22 dh5 23 lx5 25 dl5 21 cs5 27 fb5 13 ref 14 sync 8 q1 7 q2 6 q3 c4 0.1 f d1 r17 100k c3 1 f 20v v+ 29 c2 4.7 f n1 n3 n2 n4 16v d2 ec11fs1 l2 d4 1n5819 c6 330 f 10v r2 0.02 5v out +15v out c6 2.2 f 25v r16 560 c11 1 f 35v c10 1 f 35v c13 33 f 35v c1 33 f 35v batt in vppb vppa vh sync q1 q2 q3 n1n4 = si9410dy d1 = baw56l or two 1n4148s da1 da0 db1 db0 c7 150 f 10v c16 150 f 10v r1 0.025 l1 10 h d3 1n5819 c9 0.01 f c8 0.01 f r15 open figure 14. max782 ev kit schematic downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 27 figure 15. max782 ev kit top component layout and silk screen, top view downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 28 ______________________________________________________________________________________ figure 16. max782 ev kit ground plane (layers 2 an d 3), top view downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 29 figure 17. max782 ev kit top layer (layer 1), top view downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs 30 ______________________________________________________________________________________ figure 18. max782 ev kit, bottom component layout and silk screen, bottom view downloaded from: http:///
m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ______________________________________________________________________________________ 31 figure 19. max782 ev kit bottom layer (layer 4), t op view downloaded from: http:///
maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 32 __________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0 ? 1994 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. m ax 7 8 2 triple -out put pow e r-supply cont rolle r for n ot e book com put e rs ___________________________________________________ _____pa c k a ge i nform a t ion l dim a a1 b c d e e h l min 0.094 0.004 0.011 0.009 0.604 0.292 0.398 0.020 0? max 0.104 0.011 0.017 0.012 0.610 0.298 0.416 0.035 8? min 2.39 0.10 0.30 0.23 15.34 7.42 10.10 0.51 0? max 2.64 0.28 0.44 0.32 15.49 7.57 10.57 0.89 8? inches millimeters 36-pin plastic shrink small-outline package h e d a a1 c 0.127mm 0.004in. b 0.80 bsc 0.032 bsc 21-0032a e bst3 lx5 bst5 vh q3 ref d3 d2 dh5 da0 da1 db1 0. 181" (4. 597mm) 0. 132" (3. 353mm) q2 q1 vdd vppb gnd sync ss5 on5 cs5 db0 dl5 pgnd fb5 vl v+ dl3 lx3 d1 on3 ss3 cs3 fb3 dh3 vppa transistor count: 1569 substrate connected to gnd ___________________chip topogra phy _orde ring i nform a t ion (c ont inue d) * contact factory for dice specifications. 3.6v 36 ssop -40c to +85c max782sebx 3.45v 3.3v v out 36 ssop -40c to +85c max782rebx 36 ssop -40c to +85c max782ebx dice* 0c to +70c max782c/d pin-package temp. range part surface mount 0c to +70c max782evkit-so board type temp. range ev kit downloaded from: http:///

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